Method and circuit for trimming the internal timing conditions of a semiconductor memory device
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United States of America Patent
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Dec 28, 1999
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N/A
app pub date -
Feb 26, 1998
filing date -
Feb 26, 1998
priority date (Note) -
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Abstract
A method and circuit to trim the internal timing conditions for a semiconductor memory device including a memory matrix and circuit portions for allowing reading of the data stored in the memory matrix wherein such circuit portions include an ATD generator detecting each transition of a plurality of address terminals of the memory device to produce an ATD synchronization signal, a sense amplifier which receives an equalization a signal EQU from a generator activated by the ATD signal, and output buffers enabled by an OUTLATCH signal produced by a generator receiving the ATD signal and the EQU signal. The length of the signals is automatically trimmed according to a corresponding length code contained in a portion of the memory device.
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