Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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-
Dec 28, 1999
Issued Date -
N/A
app pub date -
Apr 10, 1998
filing date -
May 24, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur, an execution unit executes the family regardless of whether dependencies among the instructions in the family exist.
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