US Patent No: 6,011,406

Number of patents in Portfolio can not be more than 2000

Ultra-fast configuration mode for a programmable logic device

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Abstract

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In order to speed loading of a programming structure wherein the programmable elements in a cellular programmable logic integrated circuit (such as a field programmable gate array ('FPGA') or a programmable logic device ('PLD')) are connected in one or more series with switches interposed between elements in the series, switches are enabled and disabled in a systematic pattern to 'walk' data from the data source to a targeted programmable element. When a programmable element stores its targeted data, the switch associated with the programmable element is thereafter disabled to prevent changes in the stored data. Incrementally moving data through the series of programmable elements permits the series to reliably carry multiple data items concurrently, thereby speeding the loading process.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ALTERA CORPORATIONSAN JOSE, CA3383

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Veenstra, Kerry San Jose, CA 76 1929

Cited Art Landscape

Patent Info (Count) # Cites Year
 
ALTERA CORPORATION (4)
5,237,219 Methods and apparatus for programming cellular programmable logic integrated circuits 90 1992
5,761,099 Programmable logic array integrated circuits with enhanced carry routing 56 1995
5,825,197 Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices 5 1996
5,859,542 Programmable logic array integrated circuits with enhanced cascade 44 1997
 
SHIELDIP, INC. (1)
2004/0133,803 Methods and apparatus for protecting information 1 2003
 
XILINX, INC. (1)
4,870,302 Configurable electrical circuit having configurable logic elements and configurable interconnects 717 1988

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
ALTERA CORPORATION (12)
6,766,505 Parallel programming of programmable logic using register chains 15 2002
6,714,044 Hi-speed parallel configuration of programmable logic 7 2002
7,310,757 Error detection on programmable logic resources 43 2002
7,343,470 Techniques for sequentially transferring data from a memory device through a parallel interface 1 2003
7,328,377 Error correction for programmable logic integrated circuits 14 2004
7,317,332 Interconnection and input/output resources for programmable logic integrated circuit devices 6 2005
7,492,188 Interconnection and input/output resources for programmable logic integrated circuit devices 4 2007
7,577,055 Error detection on programmable logic resources 6 2007
8,112,678 Error correction for programmable logic integrated circuits 5 2007
7,839,167 Interconnection and input/output resources for programmable logic integrated circuit devices 1 2009
7,907,460 Error detection on programmable logic resources 2 2009
8,130,574 Error detection on programmable logic resources 0 2011
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
7,065,733 Method for modifying the behavior of a state machine 5 2003
6,996,795 Data processing in digital systems 1 2003
7,353,486 Data processing in digital systems 0 2005