
US Patent No: 6,011,406
Number of patents in Portfolio can not be more than 2000
Ultra-fast configuration mode for a programmable logic device
Stats
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Jan 4, 2000
Issued date -
Feb 20, 1998
filing date -
09/027,402
serial no -
In Force
status
Importance
Abstract
In order to speed loading of a programming structure wherein the programmable elements in a cellular programmable logic integrated circuit (such as a field programmable gate array ("FPGA") or a programmable logic device ("PLD")) are connected in one or more series with switches interposed between elements in the series, switches are enabled and disabled in a systematic pattern to "walk" data from the data source to a targeted programmable element. When a programmable element stores its targeted data, the switch associated with the programmable element is thereafter disabled to prevent changes in the stored data. Incrementally moving data through the series of programmable elements permits the series to reliably carry multiple data items concurrently, thereby speeding the loading process.
First Claim
Related Publications
International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 5,237,219 Methods and apparatus for programming cellular programmable logic integrated circuits | 90 | 1992 | |
| 5,761,099 Programmable logic array integrated circuits with enhanced carry routing | 55 | 1995 | |
| 5,825,197 Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices | 5 | 1996 | |
| 5,859,542 Programmable logic array integrated circuits with enhanced cascade | 44 | 1997 | |
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| 2002/0186,837 Multiple prime number generation using a parallel prime number search algorithm | 2001 | ||
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| 4,870,302 Configurable electrical circuit having configurable logic elements and configurable interconnects | 678 | 1988 | |