Field programmable gate array with dedicated computer bus interface and method for configuring both
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United States of America Patent
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-
Jan 4, 2000
Grant Date -
N/A
app pub date -
Jun 13, 1997
filing date -
Jun 13, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A field programmable gate array is provided which has a programmable portion and a dedicated controller-interface circuit. The programmable portion includes conventional input/output (I/O) blocks and configurable logic blocks (CLBs). The controller-interface circuit allows the FPGA to be operably coupled to an external computer bus, such as a PCI bus. The programmable portion and the controller-interface circuit are separately programmable. As a result, after the controller-interface circuit is initialized, the programmable portion can be cleared and reconfigured without having to re-initialize the controller-interface circuit. The programmable portion is programmed in accordance with an implied addressing scheme in response to a configuration bit stream.
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