Transmission-line loss equalizing circuit
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United States of America Patent
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-
Jan 4, 2000
Grant Date -
N/A
app pub date -
Jan 6, 1997
filing date -
Jun 12, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A transmission-line loss equalizing circuit includes an equalizer, a gain control circuit for controlling the gain of the equalizer based upon the peak value of an equalized output, a slicer for slicing the equalized output and outputting a data pulse, a timing extraction pulse and an equalization control pulse, a DC feedback level detector for detecting a DC component of the equalized output and feeding the DC component back to the equalizer, and an attenuating circuit provided as an initial stage of the equalizer. A plurality of .sqroot.fAGC circuits constructing the equalizer are cascade-connected and constructed by a differential non-inverting amplifier.
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