Importance

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Abstract

A synchronous clock generator is comprised of a delay-locked loop for producing a plurality of signals in response to an external clock signal. Each of the plurality of signals is delayed a predetermined period of time with respect to the external clock signal. A plurality of multiplexers is responsive to the plurality of signals for producing at least one clock signal in response to control signals input to the plurality of multiplexers. A clock driver is provided for driving the clock signal. A variable delay circuit is positioned to delay the external clock signal before input to the delay-locked loop. A compound feedback loop is responsive to certain of the plurality of signals for producing a control signal input to the variable delay circuit.

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First Claim