Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines

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United States of America Patent

PATENT NO 6013574
SERIAL NO

08906062

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Abstract

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A method of forming low resistance contact structures in vias arranged between interconnect levels is provided. The method involves interconnect lines having an anti-reflective layer formed thereupon. An interlevel dielectric layer is formed over the interconnect lines. A photoresist layer is formed over the interlevel dielectric layer and patterned to define via locations. During via etch, an organic (carbon-based) polymer layer forms upon the anti-reflective-coated interconnect lines at the bottoms of the vias. The photoresist and the etch byproduct polymer layers are then removed using a dry etch process which employs a forming gas comprising nitrogen and hydrogen. A native oxide layer subsequently forms upon the anti-reflective-coated interconnect lines when exposed to oxygen. The native oxide layer is then removed, along with any residual etch byproduct polymer, during a sputter etch procedure. Each resulting via is substantially void of polymer and oxide residue so as to present a clean via area which allows ready adherence of a plug material to the anti-reflective coating.

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Patent Owner(s)

Patent OwnerAddress
ADVANCED MICRO DEVICES INCSANTA CLARA CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Kuang-Yeh Los Gatos, CA 96 2062
Gatto, Michael J Austin, TX 2 62
Hause, Fred N Austin, TX 115 2840

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