Stackable chip scale semiconductor package with mating contacts on opposed surfaces
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United States of America Patent
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Jan 11, 2000
Issued Date -
N/A
app pub date -
Apr 1, 1998
filing date -
Nov 27, 1995
priority date (Note) -
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Abstract
A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.
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