Function block architecture for gate array
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United States of America Patent
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Jan 11, 2000
Grant Date -
N/A
app pub date -
Mar 21, 1997
filing date -
Mar 21, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.
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