Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
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United States of America Patent
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Jan 11, 2000
Issued Date -
N/A
app pub date -
Sep 24, 1997
filing date -
May 20, 1996
priority date (Note) -
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Abstract
A field programmable gate array (FPGA) comprising a matrix of programmable logic cells, a bus network of local and express bus lines, and a system of perimeter I/O pads is disclosed. Logic cells are directly connected to neighboring nearest cells, including diagonally and orthogonally adjacent cells, and are also connected to local bus lines. Such direct cell-to-cell connections allow both directions of signal propagation. I/O pads connect to cells at the perimeter of the matrix and to the bus network. Preferably, I/O pads are connectable to more than one cell and more than one row or column of bus lines, and each perimeter cell can be connected to any of several I/O pads.
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