Method and apparatus for performing N bit by 2*N-1 bit signed multiplication
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United States of America Patent
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Jan 11, 2000
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app pub date -
Mar 24, 1997
filing date -
Mar 24, 1997
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Abstract
A method and apparatus for performing N bit by 2*N (or 2*N-1) bit signed multiplication using two N bit multiply instructions. According to one aspect of the invention, a method for performing signed multiplication of A times B (where B has N bits and A has N*2 bits) is described. In this method, A.sub.high and A.sub.low respectively represent the most and least significant halves of A. According to this method, A.sub.low is logically shifted right by one bit to generate A.sub.low >>1. Then, A.sub.low >>1 is multiplied by B using signed multiplication to generate a first partial result. In addition, a second partial result is generated by performing signed multiplication of A.sub.high times B. One or both of the first and second partial results is shifted to align the first and second partial results for addition, and then the addition is performed to generate a final result representing A multiplied by B.
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