At-speed scan testing
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United States of America Patent
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Jan 11, 2000
Grant Date -
N/A
app pub date -
Jan 15, 1998
filing date -
Jan 15, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
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