Detecting long latency pipeline stalls for thread switching
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United States of America Patent
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Jan 18, 2000
Grant Date -
N/A
app pub date -
Dec 31, 1997
filing date -
Dec 31, 1997
priority date (Note) -
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Abstract
An apparatus is provided that operates in conjunction with a processor having registers and associated caches and a memory. A load management module monitors loads that return data to the registers, including bus requests generated in response to loads that miss in one or more of the caches. A cache miss register includes entries, each of which is associated with one of the registers. A mapping module maps a bus request to a register and sets a bit in a cache miss register entry associated with the register when the bus request is directed to a higher level structure in the memory system.
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