Test system with mechanical alignment for semiconductor chip scale packages and dice
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United States of America Patent
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-
Jan 25, 2000
Grant Date -
N/A
app pub date -
Dec 11, 1997
filing date -
Dec 11, 1997
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.
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