Register access controller which prevents simultaneous coupling of more than one register to a bus interface
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United States of America Patent
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Jan 25, 2000
Grant Date -
N/A
app pub date -
Dec 12, 1997
filing date -
Dec 12, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A register access controller controls the timing of coupling a selected register of a plurality of register to a bus interface during a zero-wait continuous burst transfer of data from the plurality of registers to the bus interface. During the zero-wait continuous burst transfer of data, a newly selected register is coupled to the bus interface for each clock period. The register access controller of the present invention introduces a predetermined delay time between decoupling a previously selected register from the bus interface to coupling a newly selected register to the bus interface. In this manner, the register access controller prevents coupling of two registers to the bus interface at the same time thereby reducing the risk of integrated circuit damage that may result from simultaneous coupling of multiple registers to the bus interface.
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