Stress-free shallow trench isolation
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United States of America Patent
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Feb 1, 2000
Grant Date -
N/A
app pub date -
Jan 28, 1998
filing date -
Jan 28, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A trench isolation in a semiconductor substrate is provided. The trench isolation includes a recessed region in the semiconductor substrate. The trench isolation also has a first insulator layer lining the recessed region. The first insulator aligns with the semiconductor substrate at edge of the recessed region. The trench isolation further includes a second insulator layer filling within the recessed region over the first insulator. As a preferred embodiment, the recessed region can have well rounded corners at bottom and abutting top surface of the semiconductor substrate. The first insulator has inwardly increased height after the planarization process. The second insulator layer aligns with the first insulator at inner edge of the first insulator. The second insulator layer can also have a top plain region.
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