US Patent No: 6,020,758

Number of patents in Portfolio can not be more than 2000

Partially reconfigurable programmable logic device

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Abstract

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Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ALTERA CORPORATIONSAN JOSE, CA3420

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Norman, Kevin A Belmont, CA 31 1152
Patel, Rakesh H Cupertino, CA 123 2420

Cited Art Landscape

Patent Info (Count) # Cites Year
 
XILINX, INC. (4)
5,781,756 Programmable logic device with partially configurable memory cells and a method for configuration 73 1994
5,426,378 Programmable logic device which stores more than one configuration and means for switching configurations 430 1994
5,592,105 Configuration logic to eliminate signal contention during reconfiguration 4 1995
5,760,603 High speed PLD "AND" array with separate nonvolatile memory 9 1996
 
INTEL CORPORATION (1)
5,572,707 Nonvolatile memory with a programmable configuration cell and a configuration logic for temporarily reconfiguring the memory without altering the programmed state of the configuration cell 12 1995
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5,646,544 System and method for dynamically reconfiguring a programmable gate array 281 1995
 
KEYSIGHT TECHNOLOGIES, INC. (1)
5,721,498 Block segmentation of configuration lines for fault tolerant programmable logic device 24 1995
 
MIRALFIN S.R.L. (1)
5,760,602 Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA 112 1996

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
PACT XPP TECHNOLOGIES AG (53)
7,003,660 Pipeline configuration unit protocols and communication 21 2001
7,595,659 Logic cell array and bus system 39 2001
7,444,531 Methods and devices for treating and processing data 18 2002
7,657,877 Method for processing data 40 2002
7,996,827 Method for the translation of programs for reconfigurable architectures 8 2002
7,480,825 Method for debugging reconfigurable architectures 3 2002
7,577,822 Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization 12 2002
7,434,191 Router 18 2002
8,429,385 Device including a field having function cells and information providing cells controlled by the function cells 0 2002
7,028,107 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) 47 2002
8,281,108 Reconfigurable general purpose processor having time restricted configurations 0 2003
8,127,061 Bus systems and reconfiguration methods 0 2003
6,968,452 Method of self-synchronization of configurable elements of a programmable unit 0 2003
7,036,036 Method of self-synchronization of configurable elements of a programmable module 4 2003
7,657,861 Method and device for processing data 4 2003
8,156,284 Data processing method and device 4 2003
7,394,284 Reconfigurable sequencer structure 22 2003
7,565,525 Runtime configurable arithmetic and logic cell 32 2004
7,467,296 Runtime configurable arithmetic and logic cell 0 2004
7,844,796 Data processing device and method 3 2004
8,301,872 Pipeline configuration protocol and configuration unit communication 0 2005
7,822,881 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like) 3 2005
8,250,503 Hardware definition method including determining whether to implement a function as hardware or software 1 2007
8,156,312 Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units 0 2007
7,840,842 Method for debugging reconfigurable architectures 0 2007
7,650,448 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures 37 2008
7,602,214 Reconfigurable sequencer structure 0 2008
RE44383 Method of self-synchronization of configurable elements of a programmable module 0 2008
8,209,653 Router 0 2008
8,099,618 Methods and devices for treating and processing data 1 2008
8,145,881 Data processing device and method 1 2008
8,069,373 Method for debugging reconfigurable architectures 1 2009
7,822,968 Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs 2 2009
8,058,899 Logic cell array and bus system 1 2009
8,812,820 Data processing device and method 0 2009
8,819,505 Data processor having disabled cores 0 2009
7,782,087 Reconfigurable sequencer structure 1 2009
8,686,549 Reconfigurable elements 0 2009
8,312,301 Methods and devices for treating and processing data 0 2009
8,281,265 Method and device for processing data 1 2009
7,899,962 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures 0 2009
8,726,250 Configurable logic integrated circuit having a multidimensional structure of configurable elements 0 2010
7,928,763 Multi-core processing system 0 2010
8,312,200 Processor chip including a plurality of cache elements connected to a plurality of processor cores 0 2010
8,195,856 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures 0 2010
RE45109 Method of self-synchronization of configurable elements of a programmable module 0 2010
RE44365 Method of self-synchronization of configurable elements of a programmable module 0 2010
8,686,475 Reconfigurable elements 0 2011
8,310,274 Reconfigurable sequencer structure 0 2011
8,407,525 Method for debugging reconfigurable architectures 0 2011
8,471,593 Logic cell array and bus system 1 2011
8,468,329 Pipeline configuration protocol and configuration unit communication 0 2012
8,803,552 Reconfigurable sequencer structure 0 2012
 
ALTERA CORPORATION (14)
6,182,247 Embedded logic analyzer for a programmable logic device 101 1997
6,286,114 Enhanced embedded logic analyzer 50 1998
6,247,147 Enhanced embedded logic analyzer 102 1998
6,389,558 Embedded logic analyzer for a programmable logic device 136 2000
6,754,862 Gaining access to internal nodes in a PLD 36 2001
6,460,148 Enhanced embedded logic analyzer 76 2001
6,704,889 Enhanced embedded logic analyzer 124 2002
7,036,046 PLD debugging hub 2 2002
7,076,751 Chip debugging using incremental recompilation 19 2003
7,539,900 Embedded microprocessor for integrated circuit testing and debugging 8 2003
7,206,967 Chip debugging using incremental recompilation and register insertion 7 2004
7,348,827 Apparatus and methods for adjusting performance of programmable logic devices 30 2004
7,530,046 Chip debugging using incremental recompilation 11 2006
7,864,620 Partially reconfigurable memory cell arrays 0 2009
 
XILINX, INC. (13)
6,467,009 Configurable processor system unit 165 1998
6,107,821 On-chip logic analysis and method for using the same 226 1999
6,373,279 FPGA lookup table with dual ended writes for ram and shift register modes 17 2000
6,915,518 System and method for runtime reallocation of PLD resources 2 2000
6,526,557 Architecture and method for partially reconfiguring an FPGA 69 2000
6,721,840 Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory 24 2000
6,462,579 Partial reconfiguration of a programmable gate array using a bus macro 7 2001
6,810,514 Controller arrangement for partial reconfiguration of a programmable logic device 11 2002
7,024,651 Partial reconfiguration of a programmable gate array using a bus macro 7 2002
6,920,551 Configurable processor system 1 2004
7,669,163 Partial configuration of a programmable gate array using a bus macro and coupling the third design 1 2006
7,478,357 Versatile bus interface macro for dynamically reconfigurable designs 4 2006
7,619,442 Versatile bus interface macro for dynamically reconfigurable designs 0 2008
 
Tabula, Inc. (12)
8,412,990 Dynamically tracking data values in a configurable IC 4 2007
8,525,548 Trigger circuits and event counters for an IC 4 2008
8,479,069 Integrated circuit (IC) with primary and secondary networks and device containing such an IC 4 2010
8,433,891 Accessing multiple user states concurrently in a configurable IC 4 2010
8,788,987 Rescaling 0 2011
8,760,194 Runtime loading of configuration data in a configurable IC 0 2011
8,847,622 Micro-granular delay testing of configurable ICs 0 2011
8,429,579 Translating a user design in a configurable IC for debugging the user design 4 2011
8,598,909 IC with deskewing circuits 3 2012
8,698,518 Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements 0 2012
8,760,193 Configurable storage elements 0 2012
8,755,484 Trigger circuits and event counters for an IC 0 2012
 
802 SYSTEMS LLC (2)
7,013,482 Methods for packet filtering including packet invalidation if packet validity determination not timely made 32 2000
7,031,267 PLD-based packet filtering methods with PLD configuration data update of filtering rules 38 2000
 
802 SYSTEMS, INC. (1)
8,458,784 Data protection system selectively altering an end portion of packets based on incomplete determination of whether a packet is valid or invalid 2010
 
CADENCE DESIGN SYSTEMS, INC. (1)
6,353,552 PLD with on-chip memory having a shadow register 31 2001
 
INTEL CORPORATION (1)
6,519,674 Configuration bits layout 82 2000
 
LOCKHEED MARTIN CORPORATION (1)
6,704,894 Fault insertion using on-card reprogrammable devices 6 2000
 
PACT GMBH (1)
7,237,087 Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells 54 2002
 
PACT INFORMATIONSTECHNOLOGIE GMBH (1)
8,230,411 Method for interleaving a program over a plurality of cells 2000
 
PACTXPP TECHNOLOGIES AG (1)
7,581,076 Methods and devices for treating and/or processing data 4 2002
 
SANDISK 3D LLC (1)
6,889,307 Integrated circuit incorporating dual organization memory array 17 2001
 
Tbula, Inc. (1)
8,810,277 Non-sequentially configurable IC 0 2012
 
Other [Check patent profile for assignment information] (3)
7,672,738 Programmable controller for use with monitoring device 1 2001
7,612,582 Programmable logic controller and related electronic devices 1 2007
8,869,121 Method for the translation of programs for reconfigurable architectures 0 2011