US Patent No: 6,020,758

Number of patents in Portfolio can not be more than 2000

Partially reconfigurable programmable logic device

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment, data injection circuitry are added to a FIFO architecture to allow the user to inject data at random locations without disturbing the functionality of the PLD. In another embodiment, the PLD architecture is designed to provide for address wide or frame wide accessing of configuration bits. This allows for address wide configuration and reconfiguration.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ALTERA CORPORATIONSAN JOSE, CA3991

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Norman, Kevin A Belmont, CA 31 1238
Patel, Rakesh H Cupertino, CA 101 2667

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
* 5,646,544 System and method for dynamically reconfiguring a programmable gate array 307 1995
 
MIRALFIN S.R.L. (1)
* 5,760,602 Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA 128 1996
 
KEYSIGHT TECHNOLOGIES, INC. (1)
* 5,721,498 Block segmentation of configuration lines for fault tolerant programmable logic device 26 1995
 
INTEL CORPORATION (1)
* 5,572,707 Nonvolatile memory with a programmable configuration cell and a configuration logic for temporarily reconfiguring the memory without altering the programmed state of the configuration cell 12 1995
 
XILINX, INC. (4)
* 5,781,756 Programmable logic device with partially configurable memory cells and a method for configuration 84 1994
* 5,426,378 Programmable logic device which stores more than one configuration and means for switching configurations 457 1994
* 5,592,105 Configuration logic to eliminate signal contention during reconfiguration 4 1995
* 5,760,603 High speed PLD "AND" array with separate nonvolatile memory 9 1996
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (9)
7,672,738 Programmable controller for use with monitoring device 1 2001
* 2002/0099,455 Programmable controller 20 2001
* 2006/0079,970 Programmable logic controller and related electronic devices 5 2005
* 2006/0182,108 Methods and systems using PLD-based network communication protocols 31 2006
7,612,582 Programmable logic controller and related electronic devices 3 2007
* 2008/0058,962 Programmable logic controller and related electronic devices 6 2007
* 2010/0241,823 DATA PROCESSING DEVICE AND METHOD 0 2010
* 2011/0010,523 RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL 1 2010
* 2011/0197,273 Real time firewall/data protection systems and methods 1 2010
 
PACT GMBH (2)
7,237,087 Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells 60 2002
* 2003/0056,085 Unit for processing numeric and logic operations for use in central processing units (CPUS), multiprocessor systems, data-flow processors (DSPS), systolic processors and field programmable gate arrays (FPGAS) 20 2002
 
PACT INFORMATIONSTECHNOLOGIE GMBH (1)
8,230,411 Method for interleaving a program over a plurality of cells 2 2000
 
PACTXPP TECHNOLOGIES AG (2)
7,581,076 Methods and devices for treating and/or processing data 16 2002
* 2005/0086,462 Methods and devices for treating and/or processing data 3 2004
 
Cadence Design Systems, Inc. (1)
6,353,552 PLD with on-chip memory having a shadow register 31 2001
 
802 SYSTEMS, INC. (2)
8,458,784 Data protection system selectively altering an end portion of packets based on incomplete determination of whether a packet is valid or invalid 0 2010
8,879,427 Methods for updating the configuration of a programmable packet filtering device including a determination as to whether a packet is to be junked 1 2010
 
PACT XPP TECHNOLOGIES AG (91)
* 7,003,660 Pipeline configuration unit protocols and communication 23 2001
7,595,659 Logic cell array and bus system 45 2001
7,444,531 Methods and devices for treating and processing data 19 2002
7,657,877 Method for processing data 48 2002
7,996,827 Method for the translation of programs for reconfigurable architectures 16 2002
7,480,825 Method for debugging reconfigurable architectures 5 2002
7,577,822 Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization 16 2002
7,434,191 Router 19 2002
* 2005/0053,056 Router 0 2002
8,429,385 Device including a field having function cells and information providing cells controlled by the function cells 0 2002
* 2006/0245,225 Reconfigurable elements 4 2002
7,028,107 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like) 53 2002
* 2003/0093,662 Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three-dimensional programmable cell architectures (FPGAS, DPGAS, and the like) 20 2002
8,281,108 Reconfigurable general purpose processor having time restricted configurations 0 2003
* 2006/0090,062 Reconfigurable processor 4 2003
8,127,061 Bus systems and reconfiguration methods 0 2003
6,968,452 Method of self-synchronization of configurable elements of a programmable unit 0 2003
7,036,036 Method of self-synchronization of configurable elements of a programmable module 4 2003
* 2004/0083,399 Method of self-synchronization of configurable elements of a programmable module 0 2003
* 2004/0025,005 Pipeline configuration unit protocols and communication 18 2003
7,657,861 Method and device for processing data 6 2003
* 2006/0248,317 Method and device for processing data 27 2003
8,156,284 Data processing method and device 14 2003
7,394,284 Reconfigurable sequencer structure 28 2003
* 2004/0181,726 Method and system for alternating between programs for execution by cells of an integrated circuit 1 2004
7,565,525 Runtime configurable arithmetic and logic cell 38 2004
7,467,296 Runtime configurable arithmetic and logic cell 0 2004
* 2004/0168,099 Unit for processing numeric and logic operations for use in central processing units (CPUs), multiprocessor systems 19 2004
* 2004/0243,984 Data processing method 24 2004
* 2005/0022,062 Method for debugging reconfigurable architectures 5 2004
7,844,796 Data processing device and method 3 2004
* 2005/0086,649 Method for the translation of programs for reconfigurable architectures 1 2004
* 2005/0132,344 Method of compilation 6 2005
8,301,872 Pipeline configuration protocol and configuration unit communication 2 2005
* 2005/0223,212 Pipeline configuration protocol and configuration unit communication 0 2005
7,822,881 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like) 8 2005
* 2006/0031,595 Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like 3 2005
* 2009/0031,104 Low Latency Massive Parallel Data Processing Device 8 2006
8,250,503 Hardware definition method including determining whether to implement a function as hardware or software 3 2007
8,156,312 Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units 0 2007
7,840,842 Method for debugging reconfigurable architectures 0 2007
* 2009/0006,895 Method for debugging reconfigurable architectures 4 2007
7,650,448 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures 42 2008
* 2008/0222,329 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures 0 2008
7,602,214 Reconfigurable sequencer structure 0 2008
* 2008/0191,737 Reconfigurable sequencer structure 1 2008
RE44383 Method of self-synchronization of configurable elements of a programmable module 0 2008
8,209,653 Router 0 2008
8,099,618 Methods and devices for treating and processing data 5 2008
8,145,881 Data processing device and method 1 2008
* 2009/0144,522 Data Processing Device and Method 1 2008
8,069,373 Method for debugging reconfigurable architectures 2 2009
7,822,968 Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs 2 2009
* 2009/0146,690 RUNTIME CONFIGURABLE ARITHMETIC AND LOGIC CELL 1 2009
8,058,899 Logic cell array and bus system 1 2009
8,812,820 Data processing device and method 1 2009
* 2009/0172,351 DATA PROCESSING DEVICE AND METHOD 25 2009
8,819,505 Data processor having disabled cores 1 2009
* 2009/0300,445 METHOD AND SYSTEM FOR ALTERNATING BETWEEN PROGRAMS FOR EXECUTION BY CELLS OF AN INTEGRATED CIRCUIT 3 2009
* 2009/0300,262 METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA 1 2009
7,782,087 Reconfigurable sequencer structure 1 2009
8,914,590 Data processing method and device 0 2009
8,686,549 Reconfigurable elements 1 2009
8,312,301 Methods and devices for treating and processing data 0 2009
* 2010/0153,654 DATA PROCESSING METHOD AND DEVICE 26 2009
8,281,265 Method and device for processing data 2 2009
* 2010/0070,671 METHOD AND DEVICE FOR PROCESSING DATA 1 2009
7,899,962 I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures 0 2009
* 2010/0082,863 I/O AND MEMORY BUS SYSTEM FOR DFPs AND UNITS WITH TWO- OR MULTI-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES 0 2009
* 2010/0095,094 METHOD FOR PROCESSING DATA 1 2009
8,726,250 Configurable logic integrated circuit having a multidimensional structure of configurable elements 0 2010
* 2010/0174,868 Processor device having a sequential data processing unit and an arrangement of data processing elements 0 2010
7,928,763 Multi-core processing system 11 2010
8,312,200 Processor chip including a plurality of cache elements connected to a plurality of processor cores 0 2010
8,195,856 I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures 0 2010
RE45223 Method of self-synchronization of configurable elements of a programmable module 0 2010
RE45109 Method of self-synchronization of configurable elements of a programmable module 0 2010
RE44365 Method of self-synchronization of configurable elements of a programmable module 0 2010
9,037,807 Processor arrangement on a chip including data processing, memory, and interface elements 1 2010
* 2011/0060,942 METHODS AND DEVICES FOR TREATING AND/OR PROCESSING DATA 8 2010
* 2011/0238,948 METHOD AND DEVICE FOR COUPLING A DATA PROCESSING UNIT AND A DATA PROCESSING ARRAY 8 2010
8,686,475 Reconfigurable elements 0 2011
8,310,274 Reconfigurable sequencer structure 0 2011
* 2011/0148,460 RECONFIGURABLE SEQUENCER STRUCTURE 1 2011
8,869,121 Method for the translation of programs for reconfigurable architectures 4 2011
8,407,525 Method for debugging reconfigurable architectures 1 2011
8,471,593 Logic cell array and bus system 1 2011
8,468,329 Pipeline configuration protocol and configuration unit communication 0 2012
8,803,552 Reconfigurable sequencer structure 0 2012
9,075,605 Methods and devices for treating and processing data 0 2012
9,047,440 Logical cell array and bus system 3 2013
 
RICHTER, THOMAS (1)
* 2009/0153,188 PROCESS FOR AUTOMATIC DYNAMIC RELOADING OF DATA FLOW PROCESSORS (DFPs) AND UNITS WITH TWO- OR THREE-DIMENSIONAL PROGRAMMABLE CELL ARCHITECTURES (FPGAs, DPGAs AND THE LIKE) 15 2009
 
Altera Corporation (44)
* 6,182,247 Embedded logic analyzer for a programmable logic device 110 1997
6,286,114 Enhanced embedded logic analyzer 55 1998
6,247,147 Enhanced embedded logic analyzer 113 1998
6,389,558 Embedded logic analyzer for a programmable logic device 148 2000
6,754,862 Gaining access to internal nodes in a PLD 37 2001
6,460,148 Enhanced embedded logic analyzer 90 2001
6,704,889 Enhanced embedded logic analyzer 138 2002
7,036,046 PLD debugging hub 2 2002
* 2004/0098,638 PLD debugging HUB 2 2002
7,076,751 Chip debugging using incremental recompilation 21 2003
7,539,900 Embedded microprocessor for integrated circuit testing and debugging 16 2003
7,206,967 Chip debugging using incremental recompilation and register insertion 27 2004
* 7,348,827 Apparatus and methods for adjusting performance of programmable logic devices 38 2004
7,530,046 Chip debugging using incremental recompilation 13 2006
* 8,412,990 Dynamically tracking data values in a configurable IC 10 2007
* 2009/0002,020 DYNAMICALLY TRACKING DATA VALUES IN A CONFIGURABLE IC 25 2007
8,990,651 Integrated circuit (IC) with primary and secondary networks and device containing such an IC 0 2008
* 2011/0029,830 INTEGRATED CIRCUIT (IC) WITH PRIMARY AND SECONDARY NETWORKS AND DEVICE CONTAINING SUCH AN IC 24 2008
8,525,548 Trigger circuits and event counters for an IC 13 2008
* 2011/0199,117 TRIGGER CIRCUITS AND EVENT COUNTERS FOR AN IC 15 2008
7,864,620 Partially reconfigurable memory cell arrays 1 2009
8,479,069 Integrated circuit (IC) with primary and secondary networks and device containing such an IC 13 2010
* 2011/0060,546 Intergrated circuit (IC) with primary and secondary networks and device containing such IC 27 2010
8,433,891 Accessing multiple user states concurrently in a configurable IC 11 2010
8,912,820 System and method for reducing reconfiguration power 2 2010
8,788,987 Rescaling 1 2011
8,760,194 Runtime loading of configuration data in a configurable IC 5 2011
8,847,622 Micro-granular delay testing of configurable ICs 2 2011
8,429,579 Translating a user design in a configurable IC for debugging the user design 11 2011
8,598,909 IC with deskewing circuits 8 2012
8,698,518 Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements 4 2012
8,760,193 Configurable storage elements 4 2012
9,148,151 Configurable storage elements 0 2012
8,755,484 Trigger circuits and event counters for an IC 5 2012
8,901,956 Configuration context switcher 1 2012
9,203,397 Delaying start of user design execution 0 2012
9,000,801 Implementation of related clocks 0 2013
8,935,640 Transport network 0 2013
9,257,986 Rescaling 0 2014
9,048,833 Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements 0 2014
9,018,978 Runtime loading of configuration data in a configurable IC 0 2014
9,436,565 Non-intrusive monitoring and control of integrated circuits 0 2014
9,154,134 Configurable storage elements 0 2014
9,154,137 Non-intrusive monitoring and control of integrated circuits 1 2014
 
XILINX, INC. (13)
* 6,467,009 Configurable processor system unit 185 1998
* 6,107,821 On-chip logic analysis and method for using the same 246 1999
* 6,373,279 FPGA lookup table with dual ended writes for ram and shift register modes 17 2000
* 6,915,518 System and method for runtime reallocation of PLD resources 2 2000
* 6,526,557 Architecture and method for partially reconfiguring an FPGA 69 2000
6,721,840 Method and system for interfacing an integrated circuit to synchronous dynamic memory and static memory 32 2000
* 6,462,579 Partial reconfiguration of a programmable gate array using a bus macro 7 2001
* 6,810,514 Controller arrangement for partial reconfiguration of a programmable logic device 11 2002
7,024,651 Partial reconfiguration of a programmable gate array using a bus macro 7 2002
6,920,551 Configurable processor system 1 2004
7,669,163 Partial configuration of a programmable gate array using a bus macro and coupling the third design 2 2006
7,478,357 Versatile bus interface macro for dynamically reconfigurable designs 4 2006
7,619,442 Versatile bus interface macro for dynamically reconfigurable designs 1 2008
 
SANDISK TECHNOLOGIES LLC (1)
6,889,307 Integrated circuit incorporating dual organization memory array 21 2001
 
802 Systems LLC (4)
7,013,482 Methods for packet filtering including packet invalidation if packet validity determination not timely made 36 2000
* 7,031,267 PLD-based packet filtering methods with PLD configuration data update of filtering rules 42 2000
* 2002/0080,771 Methods and systems using PLD-based network communication protocols 19 2000
* 2002/0080,784 Methods and systems using PLD-based network communication protocols 22 2000
 
INTEL CORPORATION (1)
* 6,519,674 Configuration bits layout 93 2000
 
IDEAL INDUSTRIES, INC. (1)
* 2007/0123,091 Releasable Wire Connector 1 2006
 
LOCKHEED MARTIN CORPORATION (1)
* 6,704,894 Fault insertion using on-card reprogrammable devices 6 2000
 
Tbula, Inc. (1)
8,810,277 Non-sequentially configurable IC 3 2012
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
* 2002/0016,882 Digital device, data input-output control method, and data input-output control system 4 2001
* Cited By Examiner