Sigma-delta analogue-to-digital conversion circuits
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United States of America Patent
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-
Feb 1, 2000
Grant Date -
N/A
app pub date -
Jun 24, 1997
filing date -
Jun 25, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A third-order sigma-delta analogue-to-digital conversion circuit has a filter comprising the cascaded arrangement of three individual filter circuits, a quantization circuit and a monitoring circuit. The monitoring circuit detects for a predetermined, periodic pattern in the output bit stream. The periodicity of this pattern is ##EQU1## when f.sub.c is the converter sampling frequency and f.sub.r is the resonant frequency of the filter. If the pattern is detected, the monitoring circuit resets the filter.
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