Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 1, 2000
Grant Date -
N/A
app pub date -
Sep 26, 1997
filing date -
Sep 26, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method using replication of distributed arithmetic logic circuits and recursive interpolation of reduced angular increments of sine and cosine sum constants in logic look-up tables permits the computation of vector rotation and large FFTs in an efficient-parallel fashion within a unitary field programmable gate array chip, without off-chip memory for storing constants.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully