Importance

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Abstract

This invention discloses a processor with a plurality of execution units integrated into a chip. The execution unit has an initial failure signal output device which provides an initial failure signal when there is an initial failure in its own execution unit. Further, the execution unit has an operating failure detection device which detects and provides an operating failure signal when there is a passage-of-time failure in its own execution unit. A count device for counting the number of normally operable execution units is provided which receives initial failure signals or passage-of-time failures, as fault information, from faulty execution units if any and which finds, based on the fault information, the number of normally operable execution units. An operable execution unit selection allocation device is provided which allocates, according to the fault information, instructions, only to normally operable execution units. Accordingly, failure detection of faulty execution units can be achieved in an early stage, no chips are wasted, and the processor can operate normally without troubles.

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First Claim