Method for reducing via inductance in an electronic assembly and article

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United States of America Patent

PATENT NO 6021564
SERIAL NO

09159140

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Abstract

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A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

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Patent Owner(s)

Patent OwnerAddress
W L GORE & ASSOCIATES INC555 PAPER MILL ROAD NEWARK DE 19711

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hanson, David A Altoona, WI 39 3189

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