Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack
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United States of America Patent
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Feb 8, 2000
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N/A
app pub date -
Dec 23, 1996
filing date -
Dec 28, 1994
priority date (Note) -
Expired
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Abstract
A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.
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