Semiconductor dicing and assembling method

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6022792
SERIAL NO

08815907

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

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Patent Owner(s)

Patent OwnerAddress
SII SEMICONDUCTOR CORPORATIONCHIBA-SHI CHIBA 261-8507

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akiba, Takao Chiba, JP 17 282
Inoue, Naoto Chiba, JP 95 772
Ishii, Kazutoshi Chiba, JP 26 480
Kadoi, Kiyoaki Chiba, JP 11 190
Kojima, Yoshikazu Chiba, JP 81 2743
Kuhara, Kentaro Chiba, JP 5 244
Maemura, Koushi Chiba, JP 2 139
Moya, Yasuhiro Chiba, JP 9 205
Nakanishi, Shoji Chiba, JP 13 200

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