Integrated graphics subsystem with message-passing architecture
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United States of America Patent
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Feb 15, 2000
Grant Date -
N/A
app pub date -
Mar 24, 1995
filing date -
Mar 24, 1995
priority date (Note) -
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Abstract
A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the individual units include parallel paths internally. Preferably some of the individual units are connected to look ahead by more than one stage, to keep the pipeline filled while minimizing the use of expensive deep FIFOs.
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