High speed data buffer using a virtual first-in-first-out register
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United States of America Patent
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Feb 15, 2000
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N/A
app pub date -
Aug 31, 1998
filing date -
Aug 31, 1998
priority date (Note) -
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Abstract
A dual-port, static random access memory (DPSRAM) is configured as a virtual first-in-first-out (FIFO) register under the control of a microprocessor executing a stored program or similar circuit to allow both for conventional random access data buffering between the data source and the data receiver and FIFO-type data buffering in which the data source and data receiver need not generate an address for each data word transferred, but these addresses may be automatically generated in sequence by the buffer using special circuitry.
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