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Abstract

A memory control system and method for controlling access to a global memory. The global memory has multiple memory banks coupled to a memory bus. Multiple memory controllers are coupled between processing devices and the memory bus. The memory controllers control access of the processing devices to the multiple memory banks by independently monitoring the memory bus with each memory controller. The memory controllers track which processing devices are currently accessing which memory banks. The memory controllers overlap bus transactions for idle memory banks. The bus transactions include a control bus cycle that initially activates the target memory bank and data bus cycles that transfer data for previously activated memory banks. A control bus arbiter coupled to the memory bus grants activation of the multiple memory banks according to a first control bus request signal and a separate data bus arbiter operating independently of the control bus arbiter grants data transfer requests according to a second data bus request signal.

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First Claim