Process for producing planar dielectrically isolated high speed pin photodiode

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6027956
SERIAL NO

09019079

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method is shown for producing a PIN photodiode wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication is then lapped to a obtain a preselected thickness of the intrinsic layer. And a second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
SILICON LABORATORIES INC400 W CESAR CHAVEZ AUSTIN TX 78701

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Irissou, Pierre Sunnyvale, CA 12 497

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation