IC stack utilizing secondary leadframes
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United States of America Patent
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-
Feb 22, 2000
Grant Date -
N/A
app pub date -
Jun 10, 1998
filing date -
Jun 13, 1997
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A structure and process are disclosed in which IC chip-containing layers are stacked to create electronic density. Each layer is formed by mechanically and electrically joining an IC-containing TSOP with an external leadframe. Each leadframe contains conductors which are disposed to connect with TSOP leads, transpose signals to other locations on the periphery of the TSOP, and/or connect with other layers in the stack. The TSOP/leadframe layers are stacked and joined, and the leadframe terminals of the lowest layer are disposed to facilitate connection with a PCB or other circuitry.
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