Decoder structure and method for FPGA configuration
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United States of America Patent
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Feb 22, 2000
Grant Date -
N/A
app pub date -
Dec 30, 1997
filing date -
Dec 30, 1997
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A method is provided for configuring an FPGA using a decoder implemented in the FPGA. Specifically, an external configuration device or an embedded non-volatile memory configures a first portion of the FPGA as a decoder. Encoded configuration data is transferred to the decoder, which then configures other portions of the FPGA. In one embodiment, the decoder is a decompression unit, which decompresses compressed configuration data. In another embodiment, the decoder is an interpreter, which interprets configuration commands. In some embodiments, the portion of the FPGA used for the decoder can be reconfigured after the configuration of the other portions of the FPGA.
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