Tunable delay for very high speed
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United States of America Patent
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Feb 22, 2000
Grant Date -
N/A
app pub date -
Aug 22, 1997
filing date -
Aug 22, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.
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