Importance

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Abstract

A flash memory device for providing high integration and high-speed data access has string blocks arranged in a two-dimensional manner. Each string block has a plurality of strings, at least one bit line select line, a plurality of word lines, a plurality of source line select lines, a first dual-mode line, and a second dual-mode line. Each string is constructed such that at least one bit line select transistor, a plurality of unit memory cells, and a plurality of source line select transistors are connected in series. The bit line select lines are connected to respective gates of the bit line select transistors. The plurality of word lines are connected to respective control gates of the plurality of unit memory cells. The first dual-mode line is connected to one end of each of the strings in a first string block through a bit line contact, and the second dual-mode line is connected to other end of each of the strings in the first string block through a source line contact. Additionally, the first dual-mode line is connected to the source line contact of a second string block while the second dual-mode line is connected to the bit line contact of a third string block.

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First Claim