Delay lock loop with transition recycling for clock recovery of NRZ run-length encoded serial data signals
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United States of America Patent
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Feb 22, 2000
Grant Date -
N/A
app pub date -
Mar 31, 1997
filing date -
Mar 31, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A clock recovery circuit uses a pair of variable delay lines to recover clock from a non-return to zero (NRZ) data stream. If an incoming clock transition occurs in the NRZ data, it is passed through one delay line to the output. If no incoming transition occurs, the transition at the output of the first delay line is recycled back through the second delay line. The outputs of the first and second delay lines are combined so that a transition occurs at every possible transition instant, regardless of whether a transition is present in the incoming data at the corresponding time. This permits the benefits of a delay locked loop to be achieved when using NRZ data. Applications of the clock recovery circuits to gigabit data communications systems are describe.
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