Methods of designing and fabricating intergrated circuits which take into account capacitive loading by the intergrated circuit potting material
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 22, 2000
Issued Date -
N/A
app pub date -
Mar 31, 1998
filing date -
Nov 10, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
High speed integrated circuits are designed and fabricated by taking into account the capacitive loading on the integrated circuit by the integrated circuit potting material. Line drivers may be sized to drive conductive lines as capacitively loaded by the potting material. Repeaters may be provided along long lines, to drive the lines as capacitively loaded by the potting material. Intelligent drivers may sense the load due to the potting material and drive the lines as capacitively loaded by the potting material. The thickness of the passivating layer on the outer conductive lines may also be increased so as to prevent the potting material from extending between the conductive lines. High speed potted integrated circuits may thereby be provided.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully