Self-contained memory apparatus having diverse types of memory and distributed control
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United States of America Patent
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Feb 22, 2000
Grant Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Jun 7, 1995
priority date (Note) -
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Abstract
An apparatus is provided that improves memory storage and access speed by repackaging various types of memories, SRAM, DRAM, and Disk, into a single storage unit. Each unit contains a slice of all the various memories along with programmable logic to control the accessing of the memories. This unit appears to the central processing unit (CPU) of a computer system as an extremely large secondary cache. Independent management of each unit greatly reduces bus traffic to implement any particular address space. By using a plurality of these memory units, an extremely large amount of memory can be accessed by the CPU with the speed of accessing a cache system.
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