Data processing system using a shared register bank and a plurality of processors
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United States of America Patent
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-
Feb 22, 2000
Issued Date -
N/A
app pub date -
Oct 20, 1997
filing date -
Aug 16, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method is provided for use in register-based CPUs for simultaneously processing data in a series of CPU register banks while concurrently loading and unloading data into additional register banks. The register banks then sequentially shared between arithmetic processors connected to the CPU datapath. Each register bank, after being loaded with data, is connected to a plurality of data processors in sequence and the data in each register bank is processed. The data is not moved between register banks within the datapath, except when it is loaded and unloaded from the datapath. The invention takes advantage of the shorter time required to move control signals, as compared with moving data.
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