Test circuit and system for interconnect testing of high-level packages
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United States of America Patent
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Feb 22, 2000
Grant Date -
N/A
app pub date -
Nov 24, 1997
filing date -
Oct 14, 1997
priority date (Note) -
In Force
status (Latency Note)
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Abstract
The invention relates to a test circuit and a test system which provides interconnect test capability for modules and boards. The test circuit comprises a plurality of scan chains, including a plurality of registers. The registers in each module or board are logically sorted such that identical registers are arranged successively.
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