Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines
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United States of America Patent
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-
Feb 29, 2000
Issued Date -
N/A
app pub date -
Mar 4, 1998
filing date -
Jun 5, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
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