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Abstract

A synchronous memory device includes clock receiver circuitry to receive first and second external clock signals from an external bus. Clock generation circuitry, coupled to the clock receiver circuitry, generates a first internal clock signal having a clock edge which is synchronized with at least the first external clock signal and generates a second internal clock signal having a clock edge which is synchronized with at least the second external clock signal. The memory device further includes a first subarray section and a second subarray section. The first subarray section includes a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location. The second subarray section includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section. The memory device also includes output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request. Multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first driver and couples the first internal I/O line of the second subarray section to an input of the second driver in response to a clock edge of a first internal clock signal; and couples the second internal I/O line of the first subarray section to an input of the first driver and couples the second internal I/O line of the second subarray section to an input of the second driver in response to the clock edge of the second internal clock signal.

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First Claim