Importance

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Abstract

A set of reconfigurable hardware includes a number of field programmable gate arrays (FPGAs), a controller referred to as a page manager, and a RAM-based local memory. In an illustrative embodiment, each of the FPGAs is suitable for implementing any one of a number of different portions of a logic circuit. A netlist or other descriptive information characterizing the logic circuit is partitioned into a number of pages, each of the pages corresponding to one of the portions of the circuit. The page manager controls the loading and unloading of the pages from the local memory into the FPGAs of the reconfigurable hardware, and controls storage and transfer of inter-page signals. The page manager is configured to detect 'page faults' such as, for example, an unloaded page with a full input buffer. The page manager responds to a given page fault by subsequently loading the previously unloaded page into one of the FPGAs. The page manager may include FIFO input buffers or other suitable sets of registers for storing inter-page signal values for loaded and unloaded pages.

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First Claim