Source-clock-synchronized memory system and memory unit
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United States of America Patent
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-
Mar 7, 2000
Grant Date -
N/A
app pub date -
Dec 16, 1997
filing date -
Dec 16, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.
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