Apparatus for performing multiply-add operations on packed data
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United States of America Patent
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Mar 7, 2000
Issued Date -
N/A
app pub date -
Feb 23, 1996
filing date -
Aug 31, 1995
priority date (Note) -
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Abstract
A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first, second, third, and fourth multiplier, wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder coupled to the first and second multipliers, and second adder coupled to the third and fourth multipliers. A third storage area is coupled to the adders. The third storage area includes a first and second field for saving output of the first and second adders, respectively, as first and second data elements of a third packed data.
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