Semiconductor memory device having a synchronous DRAM
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 14, 2000
Grant Date -
N/A
app pub date -
Apr 9, 1998
filing date -
Apr 9, 1997
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
This invention relates to a semiconductor memory device and uses a row address counter as well as an internal column address counter for a burst write and read. One address counter which is a combination of a refresh address counter and a burst column address counter is provided to decrease chip area and simulation time of operation waveform.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully