Bypass circuit for bypassing host computer which are connected to plurality of devices via two individual ports upon detecting lack of communication at both ports
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Mar 14, 2000
Grant Date -
N/A
app pub date -
Aug 8, 1997
filing date -
Oct 8, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.
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