Method and apparatus for detecting process sensitivity to integrated circuit layout using wafer to wafer defect inspection device
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United States of America Patent
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Mar 21, 2000
Grant Date -
N/A
app pub date -
Sep 30, 1998
filing date -
Sep 30, 1998
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus for detecting random layout structures sensitive to process induced pattern errors in semiconductor device manufacturing applies a first manufacturing process to a first wafer containing semiconductor devices. A second manufacturing process is applied to a second wafer containing semiconductor devices. The second manufacturing process is similar to, but different from the first manufacturing process. The first and second wafers are compared by image subtraction to detect systematic pattern defects in the semiconductor devices of one of the first and second wafers. After differences are detected, the layout is examined to determine whether the difference represents a defect. If so, the design rules of the layout can be changed to accommodate a wider process variation and improve processing yield.
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