Importance

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Abstract

A structure for, and a method of operating, a descriptor cache to store segment descriptors retrieved from memory. In one embodiment, the descriptor cache is direct-mapped and addressed by a first part of the physical address in memory at which a desired descriptor is stored. If the desired descriptor is not stored in the addressed entry of the descriptor cache then the descriptor is retrieved from a descriptor table held in memory and loaded into the addressed entry of the descriptor cache (which will then be able to satisfy future requests for the same descriptor). At the same time, a second part of the descriptor's physical address is loaded into an entry of a physical address cache corresponding to the addressed entry of the descriptor cache. Whenever a write to the memory occurs, the physical address cache receives the physical address written into and compares the contents of the entry of the physical address cache addressed by the first part of the physical address with the second part of the physical address. If a match occurs, the corresponding entry of the descriptor cache is modified to indicate invalidity. In this way, coherence between the descriptor tables held in memory (which may be modified) and the descriptor cache is maintained.

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First Claim