Parallel and serial debug port on a processor
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United States of America Patent
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-
Mar 21, 2000
Grant Date -
N/A
app pub date -
Dec 19, 1997
filing date -
Apr 8, 1997
priority date (Note) -
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status (Latency Note)
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Abstract
A processor has both a serial debug port and a parallel debug port. The processor includes a processor core. The serial debug port is formed of a plurality of pins configured to send and receive signals to and from external software debug equipment. The parallel debug port is formed of a plurality of pins and configured to send and receive signals from external software debug equipment. A plurality of debug registers are accessible to the serial debug port and the parallel debug port. The debug registers are also coupled to the processor core for receiving and providing debug data and control signals. The processor core performs various software debug operations in response to signals from the external software debug equipment sent over one of the parallel and serial debug ports and communicates the results of the debug operation back over one of the serial and parallel debug ports.
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