Method of forming self-aligned thin film transistor

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United States of America Patent

PATENT NO 6043113
SERIAL NO

09000153

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Abstract

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During the formation of a self-aligned thin film transistor (50), the semiconductor material channel layer (58) on the gate insulating layer (56) has a passivation shield (P.sub.S) applied to it aligned with the gate electrode (54). The channel layer is then exposed to a reagent selected to yield a chemical reaction with the portions of the channel layer (58) not covered by the passivation shield (P.sub.S) causing removal of a component of the semiconductor material thereby to change the electrical properties of those portions of the channel layer. In this manner, doped source and drain regions (60, 62) can be formed on opposite sides of the channel having edges that extend to the edges of the gate electrode avoiding any overlap therebetween and reducing the parasitic capacitance of the thin film transistor (50).

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Patent Owner(s)

Patent OwnerAddress
QED INTELLECTUAL PROPERTY LIMITEDDAWLEY ROAD HAYES MIDDLESEX UB3 1HH

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farrell, James F Etobicoke, CA 22 709

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