Planarity verification system for integrated circuit test probes
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United States of America Patent
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Mar 28, 2000
Grant Date -
N/A
app pub date -
Dec 12, 1997
filing date -
Dec 12, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A planarity verification system for proper positioning of testing probes comprises a plurality of electrical leads configured for connection to testing probes, an indicator electrically coupled to each of the leads, and a power source. One of the power source terminals is electrically coupled to the leads through the indicators and the other terminal is electrically coupled to a metalized surface such as a wafer to bias the surface. Each electrical lead forms part of a completed current path between the power source terminals when a testing probe contacts a biased surface and directs current through an associated indicator to provide an indication.
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