Addressing scheme for a double data rate SDRAM
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United States of America Patent
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Mar 28, 2000
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N/A
app pub date -
Dec 3, 1998
filing date -
Dec 3, 1998
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Abstract
A double data rate (DDR) synchronous dynamic random access memory (SDRAM) device with at least one memory bank is disclosed. Each memory bank is divided into two independent and simultaneously accessible memory planes. A unique addressing circuit controlled by an internal clock generates addresses for each plane from one external address. The generated addresses allow both planes to be accessed simultaneously. Thus, two sets of data from two independent planes of memory are simultaneously accessed in one system clock cycle.
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