Delta sigma PLL with low jitter
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Mar 28, 2000
Grant Date -
N/A
app pub date -
Aug 22, 1997
filing date -
Aug 22, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A phase lock loop circuit for a digital radio generates the sampling frequency for sampling an incoming signal by storing the samples of the incoming signal in an accumulator at a first frequency. The accumulator is unloaded at the sampling frequency. A microprocessor monitors the rate in which the samples are stored in the accumulator and provides a switching signal to vary the sampling frequency in small increments to prevent the accumulator from overflowing or underflowing.
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